1. Field of the Invention
This invention relates to semiconductor memory devices and, in particular, to output buffers of such devices. Most particularly, the invention relates to a semiconductor memory output buffer circuit having a selectable drive strength.
2. Related Art
Currently, semiconductor memory devices such as static random access memories (SRAMs) are designed so that the output buffers associated with the memory cells of a memory device have a particular drive capability (or "drive strength"). (The drive strength when the memory cell provides a logic high signal can be different than that when the memory cell provides a logic low signal.) The drive strength of an output buffer determines the amount of current available to switch the output signal from the output buffer from one state to another (i.e., from a logic high signal to a logic low signal, and vice versa), as well as the steady-state amount of current that can be supplied from the output buffer.
Memory devices can be interconnected with a variety of other electrical circuits and/or components ("receiving devices") to which the data stored in the memory device can be provided. Moreover, these receiving devices can be interconnected with a memory device in a variety of ways. Consequently, the electrical load which must be driven and switched by the output signal from an output buffer of a memory device can vary widely, depending on the particular characteristics of the receiving device and the characteristics of the interconnection between the memory device and the receiving device.
As can be appreciated, the drive strength of the output buffers of a memory device may not be appropriately matched (i.e., the drive strength may be too strong or too weak) with the electrical load presented at the output nodes of the output buffers. For example, SRAMs have typically been used in systems of electrical and/or electronic devices ("electronic systems") in which the output buffers of the SRAM were designed to drive and switch an electrical load that could be represented as a lumped capacitive load. In many current electronic systems, however, SRAMs must drive and switch electrical loads that are more accurately modelled as distributed capacitive loads (i.e., as transmission lines), rather than as lumped capacitive loads, thus necessitating output buffers having different drive characteristics.
In short, no single output buffer drive strength is appropriate for all electrical loads that an output buffer may be required to drive. For example, if the drive strength of an output buffer driving a transmission line electrical load is too strong, the impedance of the output buffer can be low enough to produce an impedance mismatch between the output buffer and the transmission line electrical load that is of sufficient magnitude to cause signal (current and voltage) reflections in the transmission line during switching. If the output buffer drive strength becomes too large, these reflections can become large enough to induce sufficient noise in the receiving device to produce failure of the electronic system of which the memory device is part ("system failure"). Further, when driving a lumped capacitive electrical load, an output buffer having a drive strength that is too large can cause excessive voltage overshoots and/or undershoots at the input buffer of the receiving device during switching. These overshoots and undershoots can also result in system failure by, for example, causing a spurious change in logic state or producing excessive noise in other devices of the electronic system (that can, in extreme cases, damage those devices). If, on the other hand, the output buffer drive strength is too small, then the data can be supplied from the memory device to the receiving device more slowly than desired, perhaps sufficiently slowly to fail to meet the timing requirements of the receiving device and thereby cause system failure.
FIG. 1 is a block diagram of a memory cell 101 and associated output buffer 102. The output buffer 102 accepts an input signal (e.g., a voltage having a particular magnitude) from the memory cell 101 at the node 103. In response to the input signal, the output buffer 102 produces an output signal (e.g., a voltage having a particular magnitude) at the node 104 that represents an input signal to a receiving device or devices.
FIG. 2A is a schematic diagram of a typical simple implementation of the output buffer 102 in which the output buffer 102 is embodied by an inverter 201. As shown in FIG. 2B, the inverter 201 can be implemented by a P-channel transistor 202 connected in series with an N-channel transistor 203 between a supply voltage and a ground voltage. In the implementation shown in FIG. 2B, the drive strength depends upon the physical characteristics of the transistors 202 and 203, only one of which is operating at any given time. Thus, as can be appreciated, in the typical output buffer implementation shown in FIG. 2B, the output buffer can have only a single drive strength when either a logic high signal or a logic low signal is received at node 103.
Previously, if a particular type of semiconductor memory device was found to have an output buffer drive strength that was incompatible with a receiving device or devices to which the memory device was to be interconnected, other types of semiconductor memory devices (e.g., memory devices made by other manufacturers) were substituted for the incompatible memory device until a memory device having an acceptable output buffer drive strength was found. However, this "solution" is inadequate if only one or a small number of memory devices are acceptable for an application because then the number of sources of memory devices for that application is undesirably limited.
Another approach has been to place a resistor between the output buffer and the receiving device. FIG. 3 is a block diagram illustrating this approach. A resistor 301 is placed between the output buffer 102 of FIG. 1 and an input buffer 302 of a receiving device. The resistor 301 reduces the current sourced to or from the output buffer 102, thus decreasing voltage overshoot and undershoot that can occur when an output buffer having an overly strong drive strength drives a lumped capacitive load. However, the addition of such a resistor adds cost to the overall electronic system. Further, if the need for such a resistor is identified after the circuit design of an electronic system has been established (e.g., during testing of the electronic system), the addition of such a resistor at that late stage may be impracticable. Moreover, the presence of such a resistor can aggravate impedance mismatching when such a strong output buffer drives a transmission line load. Additionally, the use of such a resistor does not help when the output buffer drive strength is too weak for the electrical load to be driven: in fact, the use of such a resistor exacerbates the problem of slow switching attendant an overly weak output driver.
In view of the above, it would be desirable to provide in a semiconductor memory device an output buffer circuit in which the output buffer drive strength can be varied to accommodate a variety of electrical loads. It would also be desirable to enable a user of a memory device (e.g., an assembler of an electronic system including the memory device) including such an output buffer circuit to easily select a desired output buffer drive strength.
While output buffers having selectable drive strength have previously been used with other devices, such as programmable logic devices, selectable drive strength output buffers that allow a user to adjust the output buffer drive strength have not heretofore been used with semiconductor memory devices. There are several reasons for this. First, in previous memory chips (i.e., packaged integrated circuits embodying a memory device), there have not been package leads available for inputting a control signal or signals to effect the selection of the output buffer drive strength. Moreover, programmable logic devices by their nature include a programming capability, which capability can be extended to use with output buffers; memory devices, on the other hand, have not included such capability. Second, in designing electronic systems including memory devices (e.g., personal computers), the compatibility of the memory device's output buffer drive strength with the requirements of a receiving device or devices that receive data from the memory device has not been a significant concern, since, in many cases, the degree of whatever incompatibility exists (e.g., the magnitude of the voltage undershoot and overshoot) can be tolerated. For example, the clock frequency of previous electronic systems has been relatively low (e.g., 200 MHz microprocessors are now being used in personal computers that not long ago would have used a 33 MHz microprocessor), thus allowing a longer time for an output signal from a memory device to stabilize (e.g., for voltage undershoot and overshoot to dissipate) before that signal is latched into a receiving device. Third, in a semiconductor memory device, it is typically desirable to use as high a percentage of area as possible for the memory cells, while keeping to a minimum the area used for peripheral circuitry such as output buffers, so that the memory device can be made as small as possible, thus reducing the cost per unit of memory capacity.